可規劃式維特比解碼器之設計與實現

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姓名

黃品玄(Pin-Hsun Huang ) 查詢紙本館藏

畢業系所

電機工程研究所

論文名稱

可規劃式維特比解碼器之設計與實現
(Design and Implementation of a Reconfigurable Viterbi Decoder)

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摘要(中)

維特比演算法是一種著名的最大相似演算法，這個演算法被大量使用在通道編碼、等化器與消息編碼中，因此我們希望能設計很優秀的維特比解碼器。但是，近日來「上市時間」與「完整驗證」這兩個概念日趨重要，然而使用傳統設計方法是無法同時滿足這兩個概念的需求，因為針對不同的規格同樣的模組，我們需要去重新設計與驗証。然而藉由「可規劃式設計」這個新方法，我們只需要設計一塊硬體，對於不同的規格，我們只需要重新規劃控制電路即可。
在本論文中，我們著重於可規劃式維特比解碼器的發展。我們先介紹我們所提出的可規劃式維特比解碼器。在設計的過程中，我們會探討實現上的要素且選定我們所要採用的架構；接著我們以Matlab程式驗證整個解碼運作的過程，並以Verilog硬體描述語言來模擬及驗證電路的正確性。最後，我們以Altera FLEX 10K200E來實現我們的設計。

摘要(英)

Viterbi algorithm is a famous Maximum-likelihood algorithm. This algorithm is widely used in Channel Coding, Equalizers and Source Coding. Therefore, we wish to design a high performance Viterbi decoder. But, the concepts of “Time-to-Market” and “Well-Verification” become more and more important in these days. However, there is a trade-off between these two concepts. In traditional design methodology, we must re-design the same modules for different specifications, but a new design methodology, called “Reconfigurable Design”, is introduced. By this method, we only design a fixed hardware only for different specifications. Hence, we just reconfigure the part of the control circuits in the hardware.
In this thesis, we focus on the development of the Reconfigurable Viterbi Decoder (RVD). Hence, we will introduce the concept of RVD. In the realization of RVD, we discuss the implementation issues and the proposed architecture firstly. Then, the decoding process is simulated by using Matlab and verified by Verilog HDL. Finally, the decoder is realized by the FPGA device.

關鍵字(中)

★ 可規劃式
★ 維特比演算法
★ 迴旋碼

關鍵字(英)

★ convolutional code
★ reconfigurable
★ viterbi algorithm

論文目次

CHAPTER 1INTRODUCTION1
1.1OVERVIEW OF ECC IN THE COMMUNICATION SYSTEM1
1.2CONVOLUTIONAL CODES AND VITERBI ALGORITHM2
1.3MOTIVATION AND OBJECTIVE3
1.4THESIS ORGANIZATION4
CHAPTER 2CONVOLUTIONAL CODE AND THE VITERBI ALGORITHMS5
2.1CONVOLUTIONAL CODES5
2.1.1Definition of a Convolutional Code6
2.1.2Trellis Diagram of a Convolutional Code9
2.1.3Decoding the Convolutional codes11
2.2THE VITERBI ALGORITHM12
2.2.1Definition of Viterbi algorithm13
2.2.2An example of Viterbi Decoding15
2.2.3Basic Processing Units of Viterbi Decoders18
CHAPTER 3RECONFIGURABLE VITERBI DECODERS20
3.1FIXED STATE NUMBER TRELLIS DIAGRAM AND FIXED STATE RECONFIGURABLE VITERBI DECODER20
3.2RECONFIGURABLE VITERBI DECODER27
3.2.1Floating State Reconfigurable Viterbi Decoding27
3.2.2Proof of the Floating State Reconfigurable Viterbi Decoding29
3.3METHODOLOGY OF DESIGNING A RVD35
CHAPTER 4IMPLEMENTATION ISSUES OF OUR PROPOSED RVD37
4.1IMPLEMENTATION ISSUES OF VITERBI DECODER37
4.1.1Implementation Issues of BMU37
4.1.2Implementation Issues of ACSU40
4.1.3Implementation Issues of SMU44
4.2THE STRUCTURE OF OUR PROPOSED RVD45
CHAPTER 5FPGA IMPLEMENTATIONS AND VERIFICATION50
5.1ALTERA FPGA50
5.1.1Altera FLEX10K200E51
5.1.2Altera FPGA Design Flow52
5.2IMPLEMENTATIONS OF THE PROPOSED RVD53
5.2.1Matlab Simulation Result53
5.2.2FPGA Realization57
CHAPTER 6CONCLUSION65
6.1SUMMARY65
6.2FUTURE WORKS65
REFERENCE67

參考文獻

[1]E. Biglieri, D. Divsalar, P. J. Mclane and M. K. Simon, Introduction to trellis-coded modulation with applications, Maxwell Macmillan, Canada, 1991.
[2]S. Lin and D. J. Costello, Jr., Error Control Coding, Prentice-Hall, New Jersey, 1982
[3]R. E. Ziemer, R. L. Peterson, Introduction to Digital Communication, Macmillan, New York, 1992.
[4]A. J. Viterbi, “Error Bounds for Convolutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Trans. on Information Theory, Vol. IT-13, pp. 260-269, April 1967.
[5]A. J. Viterbi, “Convolutional Codes and Their Performance in Communication Systems,” IEEE Trans. on Communication Technology, Vol. COM-19, pp. 751-772, October 1971.
[6]G. D. Forney, “The Viterbi Algorithm,” Proceedings of the IEEE, Vol. 61, pp268-278, March 1973.
[7]G. D. Forney, “Convolutional Codes II: Maximum Likelihood Decoding,” Information and Control, Vol. 25, pp. 222-226, July 1974.
[8]Andries P. Hekstra, “An alternative to metric rescaling in Viterbi decoders,” IEEE Trans. on Commu., vol. COM-37, no. 11, pp. 1220-1222, Nov. 1989.
[9]C. Shung, P. Siegel, G. Ungerbock, and H. Thapar, “VLSI Architectures for Metric Normalization in the Viterbi Algorithm,” in Proceedings of the IEEE International Conference on Communications, pp. 1723-1728, IEEE, 1990.
[10]Ivan M. Onyszchuk, “Truncation Length for Viterbi Decoding,” IEEE trans. on Commu., vol. COM-39, pp. 1023-1026, July 1991.
[11]P. J. Black and T. H. Y. Meng, “Hybrid Survivor Path Architecture for Viterbi Decoders,” in Proc. ICASSP 93, 1993, pp. I-433-I-436.
[12]J. Sparso, H. J. Jorgensen, E. Paaske, S. Pedersen and T. R. Petersen, “ An Area-Efficient Topology for VLSI Implementation of Viterbi Decoders and Other Shuffle-Exchange Type structures,” IEEE Journal of Solid-State Circuits, vol. 26, no. 2, Feb. 1991.
[13]M. Boo, F. Arguello, J. D. Bruguera, R. Doallo and E. L. Zapata, “High-Performance VLSI Architecture for the Viterbi Algorithm,” IEEE Trans. on Commu., Vol. 45, no. 2, Feb. 1997.
[14]Feng Lo, FPGA Realization of the Viterbi Decoder for HDSL2 Systems, NCU thesis, June, 2000.
[15]Y.N. Chang, Hiroshi Suzuki, K. K. Parhi, “A 2-Mb/s 256-State 10-mW Rate-1/3 Viterbi Decoder,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, Jun. 2000.
[16]P. J. Black and T. H. Meng, “A 140-Mb/s, 32-state, radix-4 Viterbi de-coder,” IEEE Journal of Solid-State Circuits, vol. 27, pp. 1877—1885, Dec. 1992.
[17]E.H, Wold, “Pipelined and parallel-pipelined FFT processor for VLSI implementation,” IEEE Trans. on Computers, vol.c-33, no.5, pp.414-426, May, 1984.
[18]P.P. Sauve, S. Crozier, A. Hunt, “High-Speed DSP Implementations of Viterbi Decoders,” see Http://www.crc.ca/fec.
[19]M. D Ciletti, Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL, Prentice-Hall Inc., New Jersey, 1999.
[20]Altera Digital Library, Altera Inc., Jan. 2000.

指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2001-6-26

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